Integrated circuits comprising semiconductor devices are used in many electronic applications, such as computers, televisions, cellular phones and other electronic devices. Integrated circuits are continually being designed in smaller dimensions, based on the demand for smaller consumer products and increased speed. Improved yields may also be achieved by reducing the area of an integrated circuit die.
A common component of an integrated circuit is a metal oxide semiconductor field effect transistor (MOSFET). As the gate length of MOSFET devices is scaled down into the sub-100 nm regime for improved performance and density, the requirements for body-doping concentration, gate oxide thickness, and source/drain doping profiles to control short-channel effects become increasingly difficult to meet when conventional semiconductor device structures based on bulk silicon (Si) substrates are utilized.
A prior art MOSFET device 100 is shown in FIG. 1a. The device 100 comprises a substrate 102 having a source 104 and drain 106 formed therein. The source 104 and drain 106 are typically formed by implanting or diffusing dopants into the semiconductor substrate 102. A gate dielectric 108 is deposited over the substrate 102, and a gate electrode 110 is formed over the gate dielectric 108. A spacer 112 is disposed adjacent each side of the gate electrode 110. A sub-surface leakage path or channel 114 resides beneath the gate electrode 110, where current is adapted to flow from the source 104 to the drain 106, for example, when the MOSFET 100 is activated.
Heavy channel 114 doping is required to provide adequate suppression of short-channel effects, which results in degraded mobility and enhanced junction leakage. The aggressive reduction of the SiO2 gate dielectric 108 thickness for reduced short-channel effects and improved drive current leads to increased direct tunneling gate leakage current and standby power consumption, and also raises concerns regarding the gate dielectric 108 reliability. For device scaling well into the sub-100 nm regime, a promising approach to controlling short-channel effects is to use an ultra-thin silicon film as the MOSFET channel 114 so that sub-surface leakage paths are eliminated.
A device structure that implements this concept is referred to as an ultra-thin body (UTB) MOSFET 200, shown in FIG. 1b. In a UTB MOSFET 200, a silicon-on-insulator (SOI) wafer is often used, comprising a substrate 202, an insulator 216 and a thin semiconductor material 218. The substrate 202 comprises a semiconductor material, and the insulator 216 is disposed over the substrate 202. The insulator 216 may comprise a buried oxide with a thickness in the range of 40 nm to 500 nm, for example. A thin film of semiconductor material 218, also referred to as a silicon body, is formed over the insulator 216. The thin semiconductor material 218 may comprise silicon with a thickness of 50 mm (or 500 Angstroms) or less, for example.
In a UTB MOSFET device 200, the source 204 to drain 206 current is restricted to flow in a region (e.g., channel 214) close to the gate electrode 210, which provides improved gate electrode 210 control. The silicon body 218 thickness tSi is typically kept below a third of the gate electrode 210 length (e.g., the horizontal length of gate electrode 210 in FIG. 1b). Because the UTB MOSFET device 200 does not rely on a heavily-doped channel 214 for the suppression of short-channel effects, the problems of mobility degradation due to impurity scattering, and threshold voltage VTH fluctuation due to the random variation of the number of dopant atoms in the channel regions of nano-scale transistors, are avoided. However, if ultra-thin source/drain regions 204 and 206 are used for the UTB MOSFET device 200, a high series resistance results that degrades the drive current. To avoid this series resistance problem, a raised source and drain structure 222 (also known in the art as an elevated source and drain structure), shown in FIG. 1c, is sometimes used. A raised or elevated source and drain device includes raised structures 222 having a thickness tS/D that are formed over the source 204 and drain 206.
There are several prior art methods of forming a raised source and drain structure 222 after the gate electrode 210 patterning step. One method includes forming raised source/drain regions 222 by poly-Si deposition followed by an etch-back process. Another method includes forming the raised source/drain structures 222 by the selective deposition of Germanium (Ge) on the source 204 and drain 206 regions. Yet another approach is to form the raised source/drain regions 222 by selective SiGe epitaxy, or by selective epitaxial growth of silicon. Another approach involves sputtering silicon over the source 204 and drain 206 regions after the gate electrode 210 and spacer 212 structures are formed. However, selective epitaxial growth of the raised source and drain regions 222 is costly, and the epitaxial growth is highly dependent on the pattern density.
What is needed in the art is an improved, cost-saving method for forming raised source and drain regions or structures of a MOSFET device.